The present invention relates in general to integrated circuit devices and is particularly directed to an improved complementary metal oxide semiconductor (CMOS) memory architecture, in which an auxiliary bipolar transistor structure is formed in a well region that is formed in common with that of a CMOS memory cell. The auxiliary bipolar transistor has an emitter region implanted separately from and with different physical characteristics than source and drain regions in the well region of the CMOS structure, so as to provide the auxiliary bipolar transistor with current gain sufficient to rupture a fusible link associated with the programming of the CMOS memory cell.
Programmable CMOS memory architectures often employ a pattern of fusible material, such as thin layer of nichrome, which is associated with each of the cells of the array and is selectively ruptured or xe2x80x98blownxe2x80x99 to establish the binary state of the cell. To blow the link, it is customary practice to force a large magnitude current through the link, which melts a relatively narrow or constricted xe2x80x98fusexe2x80x99 portion of the link, severing the link at that point, and thereby forcing the electronic state of the memory cell into a prescribed binary (1/0) condition.
A CMOS memory cell architecture in which an auxiliary bipolar transistor structure is provided for the purpose of supplying this large magnitude current is diagrammatically illustrated in FIG. 1 as comprising a semiconductor (e.g. N-type silicon) substrate 11 having a top surface 13, in respective first and second spaced portions 21 and 23 of which P-type well regions 31 and 33 are formed to a prescribed depth in substrate 11. The first P-well region 31 and adjacent N-type semiconductor material of the substrate serve as respective channels of an NMOS device 41 and a PMOS device 43 which, together, define a CMOS memory cell structure 40. To complete the CMOS device respective insulated gates 45 and 47 are formed on the surface of P-well 31 and an adjacent surface portion of N-substrate 11. Then, respective P+ source and drain regions 44 and 46 are introduced (implanted) into N-substrate 11 using gate 47 as a self-align mask. Similarly, N+ source and drain regions 48 and 49 are introduced (implanted) into P-well region 31 using gate 45 as a self-align mask. In the course of providing ohmic contacts to the respective source and drain regions of the CMOS structure, regions 46 and 48 may be bridged in common by a layer of interconnect.
To facilitate formation of the auxiliary bipolar transistor, the processing step (including mask) employed to implant the N+ source and drain regions 48 and 49 in P-well region 31 is also used to implant an N+ region 51 within P-well 33. N+ region serves as an N+ emitter region of the auxiliary transistor, shown at 50, transistor 50 being used to supply fusible link-rupturing current I, shown diagrammatically at 58, for programming the logical state of CMOS memory cell 40. The second P-well region 33 serves as the base region of transistor 50, and the underlying N-type substrate 11 serves as its collector.
In such a structure, as the packing density (lithographic line width resolution) increases, the separation between respective regions and associated PN junctions of the components of the CMOS memory cell (including the N+ emitter region 51 of the auxiliary bipolar transistor 50) decreases to the point that a parasitic thyristor device created between closely separated (PNP/NPN) regions at the surface of the substrate tends to latch up and thereby inhibit intended operation of the memory.
In order to reduce the likelihood of, and optimally prevent the occurrence of such a thyristor latch-up condition, the implant step through which the source/drain regions are formed may be tailored to reduce the impurity concentration of the source/drain regions and thereby reduce the current gain of the parasitic horizontal bipolar devices of which a respective thyristor is comprised. A drawback to this approach is the fact that reducing the implant doping concentration of the source/drain regions also reduces the doping concentration of the simultaneously formed emitter region, which reduces the current drive capability (current gain) of the auxiliary transistor to a such a low value as to effectively reduce its output current to less than that necessary to blow the fuse. (An alternative approach to eliminate the thyristor latch-up problem would be to simply increase the surface separation between regions of the architecture. An obvious, and impractical effect of increasing region separation, however, is that the intended integration density of the CMOS memory is reduced.)
In accordance with the present invention, the above described problems are solved by using a separate implant mask for the emitter region of the auxiliary transistor and controllably tailoring the geometry and impurity concentration profile of the emitter region, so that the auxiliary transistor has sufficient current gain to blow the fuse, while allowing the doping parameters of the source/drain regions of the CMOS structure to be separately established to maintain the intended integration density of the memory and prevent thyristor latch-up.
For this purpose, during the implantation of the source/drain regions form in the CMOS well region, the well region in which the auxiliary bipolar transistor is formed, is masked, so that no emitter region is formed in the well region used for the auxiliary bipolar transistor. Instead, once the source/drain regions have been formed in the well region of the CMOS device, a separate implant procedure is employed for introducing the emitter region into the well region of the auxiliary transistor. Specifically, a separate mask is used to implant the emitter region into the (bipolar base) well region of the auxiliary bipolar transistor. During this separate emitter formation step, the remainder of the substrate is masked, so that the emitter implant affects only the characteristics of the bipolar device.
Preferably, the emitter region is formed using two implants, in which a dopant of a conductivity type opposite to that of the bipolar well region is initially implanted at a relatively high energy level to a prescribed depth in the bipolar well region, followed by a second, reduced energy implant, which establishes the doping concentration of the emitter region in the vicinity of the surface of the bipolar well region, and produce a composite doping profile that optimizes the characteristics of the emitter region. Thus, the emitter region has a retrograde doping profile, with its highest concentration adjacent to the bottom of the bipolar well region. This retrograde profile, in combination with its increased depth (which results in a reduced vertical base width), yields an auxiliary bipolar structure having a current gain increased substantially with respect to that of the auxiliary bipolar transistor 50 of the structure of FIG. 1 and sufficient for programming the CMOS memory.
The architecture in which the present invention is employed may use either a planar process or a LOCOS process. In the latter case, where a bird""s beak in the field oxide at the periphery of an aperture in the field oxide through which the emitter is implanted, it is necessary to employ a separate mask that has an implant aperture the edges of which are laterally offset from the periphery of the aperture in the field oxide. This lateral spacing confines the emitter region within the active area of the bipolar well region and so as to be sufficiently spaced from material of the substrate. Otherwise, if the emitter dimensions were to be defined by the field oxide aperture, radiation upon the thin bird""s beak portion of the field oxide could initiate parasitic channel turn-on in that surface portion of the bipolar well region between the emitter region and the substrate.